Tzero Technologies develops and markets high-performance wireless networking semiconductor products. Our products utilize the ultra wideband (UWB) wireless technology and are the gold standard for UWB performance. We are always seeking high-energy individuals interested in joining our growing team.

Qualified candidates please send resumes to:jobs@tzerotech.com.

Current Openings

ASIC MAC Design Engineer
Senior ASIC Design Engineer
Senior PHY Systems Engineer
ASIC SOC Design Engineer
Systems Engineering Director

ASIC MAC Design Engineer

ASIC MAC Design Engineer is responsible for implementation of wireless MAC for high performance UWB application with integrated Phy and SOC. Baseband transceiver is a high performance multi-band OFDM mod-demod design. Candidate will be responsible for efficient implementation of multiple MAC layer protocols in hardware.Responsibilities:

• Responsible for implementing a Wireless MAC design.
• Understand the WiMedia and WUSB and Bluetooth protocols.
• Develop the microarchitecture of MAC design.
• Work with MAC algorithms and Software groups to define the hardware/software partition of the MAC protocol.
• RTL Coding of MAC design.
• Work with front end design engineers in developing timing constraints and synthesis constraints.
• Bring-up and debug of design in silicon.

Background:

• BSEE required, MSEE preferred.
• Minimum five years experience with ASIC design.
• Strong background in design of control path for MAC designs.
• Knowledge of verilog HDL.
• Background in communications is desirable.

________________________________________________

Senior ASIC Design Engineer

The Senior ASIC Design Engineer is responsible for architecture and implementation of a low power design for wireless application. Integration of digital logic with mixed signal circuits, analysis of effects of power switching on analog and digital behavior and definition of the power mode strategies to realize low power utilization in the design. The candidate will be responsible for selection and qualification of the power saving architectures and implementation and estimation of power consumption in various modes of operation. The candidate will also be responsible for ASIC flow of the design (synthesis, timing and power integrity checks), preparation of design for physical design activity.

Responsibilities:

• Analysis of power architectures and strategies for low power realizations of wireless application.
• Perform die-size and power estimates.
• Specify and Implement the power saving modes and wake-up logic.
• Synthesis of design and development of timing scripts and power integrity check scripts.
• Interface to physical design engineers from netlist to GDSII.
• Power planning (power rings/mesh), decoupling requirements.
• Timing closure flow from global route to final tapeout.
• Specify the margin requirements for timing at various stages of the flow.
• Support in timing closure with physical design engineers.
• Support with final database preparation for tape-out.

Background:

• BSEE required, MSEE preferred.
• Minimum ten years experience with synthesis and timing closure.
• Background in low power design strategies.
• Experience with backend flow is desirable.
• Knowledge of scripting languages and make flow.

________________________________________________

Senior PHY Systems Engineer

The Senior PHY Systems Engineer is responsible for implementation of advanced signal processing algorithms for a wireless PHY transceiver; generation of testvectors for verification of signal processing modules implemented onASIC; and analysis of PHY performance using simulations and testingover varying wireless environments.

Background:

• At least 3 years experience with DSP software development for communications systems.
• At least 1 year experience programming in MATLAB and C.
• Good coding skills.
• Some exposure to wirelesssystems is preferred.
• MS/PhD in EE/CS preferred.

________________________________________________

ASIC SOC Design Engineer

ASIC SOC Design Engineer is responsible for implementation of SOC for high performance UWB application with integrated Phy and MAC. Baseband transceiver is a high performance multi-band OFDM mod-demod design. Candidate will be responsible for low power realizations and power management strategies for implementation of SOC design.

Responsibilities:

• Responsible for defining the SOC architecture and power management control logic.
• Understand the interaction of WiMedia and WUSB and Bluetooth protocols with system and on-board SOC.
• Develop the microarchitecture and implement power management logic.
• Work with IP vendors for qualification and integration of peripheral logic.
• Work with MAC designers for interfacing of SOC with MAC.
• Work with front end design engineers in developing timing constraints and synthesis constraints and verification of power modes.
• Bring-up and debug of design in silicon.

Background:

• BSEE required, MSEE preferred.
• Minimum 5 years experience with ASIC design.
• Strong background in design of control logic for memory controllers and interface logic.
• Knowledge of low power design techniques a plus.
• Knowledge of verilog HDL. Knowledge of CPF/UPF formats a plus.

________________________________________________

Systems Engineering Director will manage a team responsible for advanced RF and high-speed board design, from concept to production release. You'll work with internal management to establish feasibility and scheduling of product development. Interface with vendors/ODMs to define product requirements, cost targets and ability to leverage industry expertise and resources, collaboratively achieving entitled test, yield and cost objectives.

Responsibilities:

• Reference designs with both RF and high-speed digital content, as well as FPGA implementation. Able to architect andpartition designs.
• End-to-end system design and implementation. Includes circuit design, PCB layout, BOM creation, test design development and documentation, as well as user guide development and internal user support.
• Applications (hardware/software) development, incl. definition/design/debug and system-level optimization in support of customers and technology partners
• Asia-based ODM set-up and manufacturing support, incl. board design review, ramp, test and yield. Ownership of documentation and configuration control.
• Control of system hardware, software and release/QA processes to vendors and customers.

Background:

• BSEE required, MSEE preferred.
• Five years of RF and high-speed digital board design.
• Five years experience in managing a board design team.
• Experience in implementing reference designs in Asia-based manufacturing companies.
• Knowledge of PCB design and layout tools (e.g. ORCAD, Allegro, etc.) and FPGA hardware/firmware implementation.